February 24, 2015 // By Rick Merritt

Intel will describe what it claims are some of the world's smallest DRAM and I/O circuits here this week, a testament to its 14nm process technology.

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In a preview of at least five papers at the International Solid-State Circuits Conference, one Intel executive also continued to express optimism about the companys work on 10 and 7nm nodes.

Intel will describe a 0.0500um2 SRAM bitcell capable of storing 14.5 Mbits per mm 2. At 0.6V, the 14nm cell still runs at rates up to 1.5 GHz.

The cell is part of a memory array will be widely used in Intels future SoCs such as cellular modems that use hundreds of Mbits on a die, said Kevin Zhang, an Intel fellow.

In another paper, Intel will describe a 14nm serdes transmitter that can signal rates up to 40 Gbits/s using either NRZ or PAM-4 modulation. AT 0.03 mm2, Intel claims it is the worlds smallest transmitter delivering more than 25 Gbits/s.

Another paper will report on a 10 Gbit/s serial link for PCI Express made in the 14nm process. It consumes just 59 milliwatts and takes up 0.065mm2 of silicon area.

Wafers are more complex and expensive in the 14nm process which requires double patterning and thus more masks. However, greater gains in density means overall cost per transistor continued to decline at 14nm, something Intel expects to continue for the next two nodes, said Mark Bohr, an Intel senior fellow, echoing comments made in September.

Moores Law can continue beyond 10nm with new materials and device structures and by close collaboration of process and product designers, Bohr said. I still believe 7nm without extreme ultraviolet lithography can deliver improved cost per transistor, but exactly how Im not ready to disclose, he said.

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Intel carves tiny SRAMs at 14nm