We continue our coverage this week of the International Solid State Circuits Conference (ISSCC), held in San Francisco, CA. At this event, groups from both academia and industry have gathered to present their latest and greatest research and developments. <\/p>\n
As the conference program shows, many new solid-state circuits, architectures, and processors have been revealed as well as more comprehensive performance assessments. <\/p>\n
Among the presented papers lies AMDs Zen 4c core, which may sound familiar as it has been included in recent years such as 9004 series processors or the Bergamo cloud-focused processor. This article dives into AMDs ISSCC paper to give designers more context on what the Zen 4c core offers and how AMD engineers were able to achieve it. <\/p>\n<\/p>\n
As more focus is shifted toward cloud computing, traditional approaches to processor design begin to become obsolete as number of cores can outweigh individual core performance. Conversely, edge-based devices can benefit from a small but powerful processor core. <\/p>\n<\/p>\n
These markets are where AMD hopes that the Zen 4c core can flourish. Compared to the older Zen 4 architecture, the Zen 4c is fully ISA and feature compatible, allowing for easier transitions to and from Zen 4 and Zen 4c software. In addition, the same TSMC 5 nm process is used, with more focus placed on area and power efficiency. <\/p>\n<\/p>\n<\/p>\n
In terms of features, the Zen 4c core is highly similar to the normal Zen 4, with the primary deviation appearing in the L3 cache. Compared to Zen 4, the Zen 4c core only has 2 MB L3 cache compared to Zen 4s 4 MB. This tradeoff is compensated for, however, due to the increased number of cores allowed with the Zen 4c core architecture. <\/p>\n<\/p>\n
In order to support high-core-count dies, Zen 4c required aggressive optimization. In each SRAM cell, two transistors were shaved off by using a double-pumped architecture to perform reads and writes in one clock cycle. This allowed for a 40% macro area reduction while only reducing the clock speed by 20%. <\/p>\n<\/p>\n<\/p>\n
While a lower clock frequency isnt necessarily a good thing, the lower clock ultimately means more area and power reduction per core due to 50% decreased leakage and 25% less switching capacitance. Ultimately, the Zen 4c core reported a 35% smaller core area in the same process node. <\/p>\n
The increased area efficiency ultimately allowed AMD engineers to double the core count on a Zen 4c chiplet while maintaining the same amount of L3 cache and with only a 10% total area increase. <\/p>\n<\/p>\n<\/p>\n
The resulting Zen 4c chiplet touted a 9% performance improvement over Zen 4 chiplets, showing the cores effectiveness in compute applications. Normalized to area and power, the Zen 4c shows a 25% and 9% improvement over Zen 4 architectures, paving the way for better and more efficient high-core-count processors in cloud computing applications. <\/p>\n<\/p>\n
Designers curious about the performance of Zen 4c cores can look to AMD EPYC 9004 series processors or 7000 series of mobile processors to evaluate the performance of the new cores. From what we know now, we can see that the Zen 4c cores excel in applications where efficient computing is required. <\/p>\n<\/p>\n
All images used courtesy of ISSCC and AMD <\/p>\n
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ISSCC 2024: Inside AMD's Zen 4cThe Area-Optimized Cloud Computing Core - News - All About Circuits<\/a><\/p>\n","protected":false},"excerpt":{"rendered":" We continue our coverage this week of the International Solid State Circuits Conference (ISSCC), held in San Francisco, CA. At this event, groups from both academia and industry have gathered to present their latest and greatest research and developments. As the conference program shows, many new solid-state circuits, architectures, and processors have been revealed as well as more comprehensive performance assessments Continue reading