Next-generation system-level design platform integrates Forte and Cadence technology <\/p>\n
HIGHLIGHTS: <\/p>\n
- Industry's first high-level synthesis platform that can be utilized across an entire system-on-chip (SoC) design <\/p>\n
- First silicon-proven high-level synthesis platform to address real world challenges, including ECO, low power, IP reuse, and routing congestion <\/p>\n
- Consistent environment from TLM through gates improves design and verification quality <\/p>\n
SAN JOSE, Calif. -- Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the Cadence() Stratus(TM) high-level synthesis platform, the industry's first high-level synthesis platform that can be utilized across an entire system-on-chip (SoC) design. This next-generation platform integrates Forte Cynthesizer((TM)) and Cadence C-to-Silicon Compiler into one tool to deliver 10X productivity improvement, 20 percent better power, performance, and area (PPA) quality of results (QoR), and 5X faster verification versus a hand-written RTL flow. <\/p>\n
The Stratus high-level synthesis platform is currently available. For more information, visit http:\/\/www.cadence.com\/news\/stratus<\/a>. <\/p>\n Prior to the Stratus platform, no high-level synthesis tool was robust enough to be used across an entire SoC design, and designers were forced to choose the parts of their designs in which they would utilize the technology. With the Stratus platform, Cadence has eliminated that design compromise by integrating a comprehensive set of features into one platform, including: <\/p>\n -- A sixth generation high-level synthesis core engine to provide excellent usability, scalability, and QoR across the full application space, including both control-centric and datapath-centric designs containing hundreds of blocks -- Full integration with Cadence Encounter RTL Compiler and Cadence Encounter() Conformal() ECO Designer to allow physically-aware and ECO-aware high-level synthesis and minimize implementation changes from Engineering Change Orders -- Rich intellectual property library of I\/O interfaces and customizable floating point datatypes to increase productivity by giving designers synthesizable optimized SystemC building blocks -- Full IDE and automation of tool flow and multiple scenario evaluation to enable full architectural exploration, and improve verification by providing a consistent environment from early TLM models through gates <\/p>\n \"With our high-level synthesis flow and the Stratus platform, we're now doing the kinds of things that we couldn't have imagined doing previously,\" said Ray McConnell, chief technology officer of Blu Wireless Technology. \"For example, we can now have a working prototype of a complete multi-gigabit modem with a mmwave beamsteering antenna available when we're doing the integration and system and software validation. Previously, we would have had to use poor approximations for early validation. Having an early working prototype is having a significant business impact in terms of our potential customers' enthusiasm and confidence.\" <\/p>\n <\/p>\n More: <\/p>\n EDA Software offers system-level design\/synthesis platform.<\/a><\/p>\n","protected":false},"excerpt":{"rendered":" Next-generation system-level design platform integrates Forte and Cadence technology HIGHLIGHTS: - Industry's first high-level synthesis platform that can be utilized across an entire system-on-chip (SoC) design - First silicon-proven high-level synthesis platform to address real world challenges, including ECO, low power, IP reuse, and routing congestion - Consistent environment from TLM through gates improves design and verification quality SAN JOSE, Calif. Continue reading